The present invention relates to a cascode amplifier, and more particularly, to a cascaded amplifier and method for controlling a current of the cascode amplifier.
FIG. 1 is a diagram illustrating a conventional cascode current mirror 100. The cascode current mirror 100 includes four transistors M1-M4 and a current source I1. The function of the cascode current mirror 100 is to make the transistors M1 and M2 replicate (or mirror) currents flowing through the transistors M3 and M4 (i.e., current provided by the current source I1). However, in the cascode current mirror 100, the transistors M2 and M4 may not be operated in the same region: for example, the transistor M2 is in a saturation region of operation while the transistor M4 is in a triode region of operation. As a result, voltage levels of nodes N2 and N4 may not be close to each other, and a voltage level of a node N1 thus could not track to a voltage level of a node N3, causing the currents of the transistors M1 and M2 to not well correspondingly mirror the current provided by the current source I1.
In addition, short channel devices, of which the channel has the minimum length in its design rule, are typically chosen in order to achieve good amplifier performance, such as gain and noise figure (NF). However, a transistor with a shorter channel length is more likely to suffer from the well-known channel-length modulation effect. FIG. 2 shows an Id-VDS characteristic of the transistor, where Id is a current of the transistor and VDS is a voltage difference between drain and source electrodes of the transistor. With a serious channel-length modulation effect, Id rapidly increases with VDS (i.e., a slope of a curve 210 is great when the transistor operates in the saturation region). Therefore, in deep sub-micro process, even when both the transistors M4 and M2 operate in the saturation region, it is hard to keep a stable current mirror ratio because of the short channel length. That is, currents of the transistors M1 and M3 may not meet the request due to the disparity between the voltages of the nodes N2 and N4 shown in FIG. 1.